1. Field of the Invention
This invention relates in general to semiconductor devices and more specifically to transistors.
2. Description of the Related Art
As transistors shrink in dimension, the ability to scale down the gate length of a conventional bulk silicon MOSFET diminishes due to the Short Channel Effect (SCE). Single Gate Fully Depleted Semiconductor-on-Insulator (FDSOI) technology has been established as one solution to reduce Short Channel Effect as well as to reduce un-wanted parasitic capacitances. However, Single Gate FDSOI technology may require stringent thickness and uniformity control of the thin silicon film on insulator to achieve full depletion. Furthermore, the Drain-Induced Virtual Substrate Biasing (DIVSB) effect is another challenge for Single Gate FDSOI technology. In contrast, Double-Gate FDSOI technology may require a less stringent requirement on the thickness of a semiconductor on insulator, may reduce the Drain Induced Virtual Substrate Biasing (DIVSB) effect, and may maintain better Short Channel Effect (SCE) control and high transconductance. However, it has been difficult to build a simple, manufacturable planar Double Gate FDSOI transistor with good alignment between the top gate and bottom gate.
What is needed is an improved method that can be used in forming a multiple gate transistor.
The use of the same reference symbols in different drawings indicates identical items unless otherwise noted. The figures are not necessarily drawn to scale.